The matter in this application corresponds to the matter contained in Disclosure Document 446,511, filed Oct. 26, 1998, wherein this application assumes the priority date of that document.
1) Field of the Invention
In general, the present invention relates to the design and manufacture of circuits containing phase lock loops. More particularly, the present invention relates to the circuit design of CMOS and BICMOS circuits that contain phase lock loops with on-chip loop filters.
2) Description of the Prior Art
In the prior art record, there are many phase lock loop circuits that are manufactured using CMOS and BICMOS manufacturing processes. The uses of CMOS and BICMOS manufacturing processes have many known advantages and disadvantages. Among the disadvantages is the inability to manufacture precision components with highly accurate absolute values. In many circuit designs, the circuit is engineered so that only the ratio of components needs to be accurate. In this manner, the importance of the accuracy of any one component is minimized. However, in design of the xe2x80x98Loop Filterxe2x80x99 in a phase lock loop, there is often a single resistor. It is highly desirable to manufacturer this resistor on-chip. By manufacturing the resistor on-chip, an external component is eliminated and the power can be reduced. The reduction in power results from the fact that currents can be lowered because the parasitic effects are much reduced with the resistor on-chip. However, if this resistor is manufactured using a CMOS or a BICMOS process, the variation in this resistor can be on the order of +/xe2x88x9250% or more over process and temperature. This is problematic because both the lock up time and the jitter of a phase lock loop are functions of the process and the temperature. This causes system performance to vary from manufactured lot to manufactured lot, and within each lot the system will vary as a function of temperature.
A common practice in CMOS and BICMOS processing is to laser trim the resistors used within a circuit to the values needed. This results in a precise resistor value within the circuit. Laser trimming is a time consuming and expensive process. In addition, the trimming process does not compensate for the change in resistor value that occurs when the temperature of the resistor changes. Changes in temperature can cause a CMOS resistor value to vary by +/xe2x88x9250%.
Most, if not all, of the existing techniques for incorporating an on-chip CMOS resistor into the loop filter of a phase lock loop, results in either process variation in the resistor or additional manufacturing using laser trimming. The temperature variation in the resistor is not addressed by laser trimming procedures. Therefore, even with laser trimmed circuits, the system performance of that circuit will vary widely with changes in temperature. This variation often forces the loop filter of a phase lock loop off the chip in order to meet design requirements. The off-chip design significantly increases the cost of the phase lock loop and the degree of power consumption.
A need therefore exists for a circuit design and associated method of manufacturing on-chip loop filters that are within exact performance parameters that remain stable across both process and temperature, thereby decreasing the lock-in time and improving the bit error rate in data recovery circuits used in many types of data storage and communication systems. This need is met by the present invention as described and claimed below.
An improved loop filter device for use in a phase lock loop that improves lock-in time and cycle-to-cycle jitter in the phase lock loop. The loop filter is used in a phase lock loop circuit having a phase frequency detector, a charge pump, a voltage controlled oscillator and a divider. The loop filter has a first capacitor with a first side and a second side, wherein the first side of the first capacitor is coupled to the output of the charge pump and the input of the voltage controlled oscillator. A CMOS switch is coupled to the second side of the first capacitor, wherein the CMOS switch is selectively operable between an open condition and a closed condition. At least one second capacitor is coupled in parallel with said switch, wherein the first capacitor is joined in series with said at least one second capacitor when the CMOS switch is in its open condition. The operation of the CMOS switch is controlled by the output of the phase frequency detector or some other dynamic loop parameter that is indicative of a phase of frequency error.